1. Field of the Invention
The present invention relates to a method for fabricating semiconductor devices, and more particularly to a method for forming contacts of semiconductor devices, in which an oxidized silicon-rich nitride film is used as an etch barrier film in a self-aligned contact (SAC) process conducted using the etch barrier film, thereby being capable of avoiding a degradation in the quality of devices finally produced due to a short circuit of conductive lines, an etching stop caused by a reduced process margin, and stress occurring during the SAC process, so as to achieve an improvement in a yield process and an improved reliability in the operation of the devices.
2. Description of the Prior Art
The recent trend to fabricate highly integrated semiconductor devices has been greatly affected by the development of techniques of forming patterns having a micro dimension. In other words, in order to fabricate highly integrated semiconductor devices, it is necessary to form photoresist film patterns having a micro dimension. Such photoresist film patterns are widely used as masks for carrying out an etch process or ion implantation process in the fabrication of semiconductor devices.
Although the resolution of such a photoresist film pattern is greatly affected by the material of the photoresist film and the bondability of the photoresist film to a substrate, on which the photoresist film is formed, it is basically proportional to the wavelength of light emitted from a light source used in a stepper and a process constant used while being inversely proportional to the numerical aperture of the stepper. That is, the resolution can be expressed by the following equation: EQU R=k.times.8/NA
where, R represents a resolution, k represents a process constant, 8 represents the wavelength of light emitted from a light source used in a stepper, and NA represents the numerical aperture of the stepper.
In order to obtain an improvement in the resolution of the stepper, it is necessary to use a light source having a reduced wavelength. For example, G-line steppers using a wavelength of 436 nm and i-line steppers using a wavelength of 365 nm are limited in terms of resolution to about 0.7 m and about 0.5 m for line/space patterns. In order to form micro patterns having a dimension of less than 0.5 m, it is necessary to use a stepper using a light source having a wavelength shorter than those of G or i-line steppers. Such a light source may be a deep ultraviolet (DUV) source such as a KrF laser having a wavelength of 248 nm or an ArF laser having a wavelength of 193 nm.
In addition to attempts to improve steppers as mentioned above, improvements in processes have also been made in order to improve a limitation in resolution. For example, an use of a phase shift mask as a photo mask has been proposed. In addition, a contrast enhancement layer (CEL) method has been developed in which a separate thin film capable of achieving an improvement in an image contrast is formed on a wafer. A tri-layer resister (TLR) method has also been proposed in which an intermediate layer made of, for example, spin on glass (SOG), is interposed between two photoresist films. Also, a sililation method has been proposed in which silicon is selectively implanted in an upper portion of a photoresist film.
Meanwhile, contact holes, which are adapted to connect upper and lower conductive lines to each other, exhibit a high design rule, as compared to line/space patterns. For an increased integration degree of semiconductor devices, such contact holes have a reduced size and a reduced space from peripheral lines. Furthermore, an increase in an aspect ratio is involved. The aspect ratio represents the depth-to-diameter ratio of a contact hole.
For this reason, where a highly integrated semiconductor device having a multi-layer conductive line structure is to be fabricated, an accurate and strict alignment among masks is required in the fabrication of the semiconductor device. This results in a reduction in a margin process.
Masks for the formation of such contact holes are formed, taking into consideration a misalignment tolerance involved in the process of aligning those masks with one another, a lens distortion involved in a light exposure process, a critical dimension variation involved in the process of forming those mask and conducting a photolithography, and a registration among those masks, in order to maintain a desired space between adjacent contact holes.
For such a contact hole formation method, there have been proposed a direct etch method, a method using side-wall spacers, and an SAC (self align contact) method.
The direct etch method and the method using side-wall spacers exhibit a limitation involved in the fabrication of highly integrated semiconductor devices because they cannot be applied to the fabrication of semiconductor devices involving a design rule of 0.3 m or less in accordance with current techniques.
The SAC method has been proposed in order to overcome a limitation involved in a lithography used in the formation of contact holes. Known SAC methods are classified in accordance with an etch barrier film used. For such an etch barrier film, a polysilicon film, a nitride film, and an oxidized nitride film. A preferred one is an SAC method using a nitride film as an etch barrier film.
Now, various examples of conventional methods for forming self-aligned contacts of semiconductor devices will be described in detail.
In accordance with one example of a conventional method for forming self-aligned contacts of semiconductor devices, a desired underlayer structure is formed on a semiconductor substrate. The underlayer structure may include a device isolation oxide film, and metal oxide semiconductor field effect transistors (MOSFETs) each including a gate electrode and a source/drain region overlapping with a gate oxide film and a mask oxide film pattern, respectively. Over the entire exposed upper surface of the resulting structure, an etch barrier film and an interlayer insulating film made of an oxide material are then sequentially formed.
Thereafter, a photoresist film pattern is formed on the resulting structure in order to expose portions of the interlayer insulating film corresponding to regions where contacts for charge storage electrodes and bit lines, etc. are to be formed, respectively.
The interlayer insulating film is then dry-etched at its exposed portions not covered with the photoresist film pattern, thereby causing the etch barrier film to be partially exposed. The etch barrier film is subsequently etched at its exposed portions, thereby forming contact holes.
Where the etch barrier film is made of polysilicon, the formation thereof may be carried out using a method, in which the etch barrier film is completely formed over the entire surface of the semiconductor substrate, or a method in which the etch barrier film is formed in the form of pads on portions of the semiconductor substrate corresponding to the contact hole forming regions, respectively.
Since polysilicon, which exhibits an etch mechanism different from that of oxide, is used to form the etch barrier film, it is possible to obtain a high etch selectivity difference with regard to the oxide films disposed therebeneath.
However, the poly barrier SAC formation method exhibits a degradation in reliability in regard to the insulation among contact holes. On the other hand, the pad formation method involves a damage of the silicon substrate occurring when the contact pads are misaligned from the silicon substrate.
In order to solve the above-mentioned problems, formation of spacers or expansion of contact pads has been proposed. However, these methods involve a problem in that they cannot realize a design rule of 0.18 m or less.
The SAC method using a nitride film as an etch barrier film (poly barrier SAC) is known as a method capable of solving the above mentioned problems.
In accordance with this SAC method, the interlayer insulating film is dry-etched under the condition in which the etch selectivity difference between the interlayer insulating film and the etch barrier film is 15:1 or more, thereby causing the nitride film to be partially exposed. The exposed portions of the nitride film are then removed, thereby forming contact holes.
In this case, the etch process is carried out using one or more of C.sub.2 F.sub.4, C.sub.2 F.sub.6, C.sub.3 F.sub.6, C.sub.3 F.sub.8, C.sub.4 F.sub.8, C.sub.2 H.sub.2, CH.sub.3 F, CH.sub.3 F, CH.sub.2 HF, and CH.sub.2 F.sub.2, as C--H--F-based gas or hydrogen-containing gas producing a large amount of polymer, mixed with inert gas, in order to obtain an increased etch selectivity.
As a polymer produced during the etch process is deposited on the interlayer insulating film made of an oxide material, it is continuously removed by oxygen generated from the oxide film, so that the interlayer insulating film is etched. However, where the polymer is deposited on the nitride film, this nitride film is not damaged because there is no etch source.
Therefore, although an increase in the amount of polymer produced results in an increase in the etch selectivity difference between the oxide film and the nitride film, an excessive production of polymer or a production of a polymer containing non-etchable components may cause stopping of the etch process at a certain stage. When etching gas of an increased C/F ratio is used, an increased production of polymer occurs, thereby causing a easier stopping of the etch process.
On the other hand, where an excessively reduced etch selectivity difference between the oxide film and the nitride film, a damage of the nitride film may occur. In this case, the conductive layer, disposed beneath the nitride film, for example, the semiconductor substrate, may be damaged. A short circuit between upper and lower lines may also be generated. The above method also exhibits a limited process tolerance for optimum process conditions, a reduced reproducibility, and a degraded reliability resulting from stress applied to other layered films.
The method using an oxidized nitride film as an etch barrier film is a method proposed to solve the problems involved in the SAC method using a nitride film as an etch barrier film.
The oxidized nitride film serves to prevent an application of stress to layers disposed therebeneath and a damage of the interface thereof with a boro phospho silicate glass (BPSG) film.
However, this method involves a problem of having a difficulty in conducting a desired SAC process itself because oxide nitride exhibits medium properties between oxide and nitride, so it is difficult for the oxidized nitride film to have a desired high etch selectivity of, for example, 15:1 or more, to the oxide film.
Another conventional method for forming self-aligned contacts of semiconductor devices will be described hereinafter.
FIGS. 1 to 3 are cross-sectional views respectively illustrating a conventional method for forming self-aligned contacts of semiconductor devices.
In accordance with this conventional method, a conductive layer 11 is first formed over a semiconductor substrate (not shown) in order to form word lines, bit lines, or other metal lines on the semiconductor substrate, as shown in FIG. 1. An anti-reflection film and a hard mask 15 are then sequentially deposited over the conductive layer 11.
The anti-reflection film 13 is comprised of an oxidized silicon nitride film whereas the hard mask 15 is comprised of a nitride film formed using a plasma enhanced chemical vapor deposition (PECVD) process.
As shown in FIG. 2, a photoresist film pattern 17 for contacts is formed on the nitride film adapted to form the hard mask 15.
The photoresist film pattern 17 may be formed with scum. The formation of such scum results from amines produced due to a reaction of the photoresist film 17 with nitrogen generated from the nitride film at a subsequent process for forming the hard mask 15. This scum results in formation of photoresist film pattern tails 19 adversely affecting a subsequent formation of conductive lines.
An CN-SAC method using a capping nitride may be conducted prior to the formation of the photoresist film 17. This CN-SAC method may be effectively carried out by virtue of a high etch selectivity difference of the capping nitride from the oxide film.
However, this method involves a problem resulting from intrinsic stress of the nitride film. That is, it is impossible to reduce cracks formed during a process for forming conductive lines due to the intrinsic stress of the nitride film. Such cracks may cause a degradation in the characteristics of the conductive lines. For this reason, the final devices are adversely affected.
Prior to the formation of the photoresist film pattern 17 shown in FIG. 2, the nitride film deposited for the hard mask 15 is processed at its surface using plasma, thereby forming a silicon oxide film 21 thereon.
After forming a mask for conductive line contacts on the silicon oxide film 21, the oxide film 21, hard mask 15, anti-reflection film 13, and conductive layer 11 are etched using the mask, thereby patterning them.
Thereafter, nitride film spacers are formed on side walls of the pattern of the conductive layer 11 using a low pressure chemical vapor deposition (LPCVD) process.
The nitride film spacers advantageously exhibit a high step coverage. However, these nitride film spacers exhibit a low bonding force to the PECVD nitride film adapted to be used as the hard mask, so that they may be detached from the PECVD nitride film in a subsequent thermal process. In this case, an oxidation of the conductive layer 11 may occur.
As apparent from the above description, the conventional method for forming contacts of semiconductor devices involves various problems.
That is, since the anti-reflection film, hard mask, and insulating film spacers are different from one another in terms of materials used therefor or deposition methods therefore, the conventional method may involve a peel-off phenomenon occurring between interfaces of those films. For this reason, unnecessary oxide films may be formed resulting in a degradation in the throughput, characteristics, and reliability of the final semiconductor devices.
Another conventional method for forming self-aligned contacts of semiconductor devices will be described hereinafter.
FIG. 4 is a cross-sectional view illustrating a conventional method for forming self-aligned contacts of semiconductor devices.
In accordance with this method, a conductive layer 33 for gate electrodes is first formed over a semiconductor substrate 31, as shown in FIG. 4. A first silicon nitride film 35 as a mask insulating film is then formed over the conductive layer 33.
Thereafter, an oxidized silicon nitride film 39 is formed as an anti-reflection film over the first silicon nitride film 35.
An etching process using a gate electrode mask is subsequently carried out. In this etching process, the oxidized silicon nitride film 39 as an anti-reflection film, the first silicon nitride film 35 as a mask insulating film, and the conductive layer 33 for gate electrodes are etched, thereby forming gate electrodes.
In the fabrication of highly integrated semiconductor devices as in this case, it is essentially necessary to use the anti-reflection film because the silicon nitride film adapted as a mask insulating film exhibits a severe diffused reflection.
A second silicon nitride film 37 is then formed on the side walls of the gate electrodes, thereby forming insulating film spacers on those side walls.
Subsequently, an interlayer insulating film 41 is formed to planarize the entire upper surface of the resulting structure. The interlayer insulating film 41 is made of an insulating material, exhibiting a fluidability, such as BPSG.
An SAC process is then conducted in which contact holes 43 allowing desired portions of the semiconductor substrate 31 to be exposed are formed.
In accordance with this conventional method, however, the wafer used may be subjected to a distortion resulting from high stress of the mask insulating film or the silicon nitride film used for insulating film spacers. Such a wafer distortion may cause a lifting phenomenon of the conductor.
As a result, there is also a problem, such as alignment between different layers, of difficulty in conducting a subsequent lithography process.
Furthermore, the silicon nitride film may degrade the characteristics of the final devices because it has a high parasitic capacitance around the conductor by virtue of its high dielectric constant.
Since the silicon nitride film also exhibits a severe diffused reflection, it essentially requires to use an anti-reflection film disposed thereover. Such a requirement results in a complexity of fabrication processes.